1. Field of the Invention
The present invention relates to a dielectric separation type semiconductor device which includes a dielectric layer and a back-surface electrode provided on a top surface and a bottom back surface, respectively, of a semiconductor substrate. Further, the present invention is concerned with a method of manufacturing the dielectric separation type semiconductor device as well.
2. Related Art
A variety of dielectric separation type semiconductor devices have heretofore been proposed. Byway of example, reference may have to be made to Japanese Patent No. 2739018 (FIGS. 52 to 57).
As is shown in FIGS. 52 and 53 of the publication mentioned above, a dielectric layer and a back-surface electrode are provided on a top surface and a bottom or back surface, respectively, of a semiconductor substrate in the dielectric separation type semiconductor device disclosed in the above-mentioned patent, wherein an n−-type semiconductor layer is provided on the top surface of the dielectric layer.
The dielectric layer isolates dielectrically the semiconductor substrate and the n−-type semiconductor layer from each other, wherein the n−-type semiconductor layer is delimited to a predetermined range by an insulation film.
In the predetermined range mentioned above, an n+-type semiconductor region of a relatively low resistance value is formed on the top surface of the n−-type semiconductor layer. Further, a p+-type semiconductor region is so formed as to surround the n+-type semiconductor region. A cathode electrode and an anode electrode are contacted to the n+-type semiconductor region and the p+-type semiconductor region, respectively, wherein the cathode electrode and the anode electrode are insulated from each other by an interposed insulation film.
As shown in FIG. 54 of the aforementioned Japanese Patent No. 2739018, when a voltage of positive (plus) polarity applied to the cathode electrode is gradually increased in the state where the anode electrode and the back-surface electrode are each set to the zero potential (zero volt or 0 V), a depletion layer extends or spreads from a pn junction formed between the n−-type semiconductor layer and the p+-type semiconductor region. In this state, the semiconductor substrate is fixed to the ground potential and serves as a field plate through the medium of the dielectric layer. Consequently, in addition to the depletion layer mentioned above, an additional depletion layer spreads from a boundary between the n−-type semiconductor layer and the dielectric layer toward the top surface of the n−-type semiconductor layer.
Owing to the extension of the additional depletion layer, the first mentioned depletion layer tends to spread toward the cathode electrode, as a result of which the intensity of the electric field at the pn junction between the n−-type semiconductor layer and the p+-type semiconductor region is mitigated or reduced. This effect is generally known as the RESURF (REduced SURface Field) effect.
As is described in the aforementioned patent by reference to FIG. 55, with the distribution of electric field intensity at a section sufficiently distanced from the p+-type semiconductor region, the total voltage drop V making appearance at the section mentioned above can be represented by the following expression (3)V=q·N/(∈2·∈0)×(x2/2+∈2·t0·x/∈3  (3)where x represents the width of the additional depletion layer in the vertical direction, t0 represents the thickness of the dielectric layer, N represents the impurity concentration [cm−3] of the n−-type semiconductor layer, ∈0 represents the dielectric constant of vacuum [C·V−1·cm−1], ∈2 represents the relative dielectric constant of the n−-type semiconductor layer and ∈3 represents the relative dielectric constant of the dielectric layer. In this conjunction, it is presumed that the top surface of the n−-type semiconductor layer is located at the origin of the abscissa in the distribution of electric field intensity mentioned above.
It can be seen from the expression (3) that the width x of the additional depletion layer in the vertical direction decreases when the thickness t0 of the dielectric layer is increased while maintaining the total voltage drop to be constant. This means that the RESURF effect becomes enfeebled.
On the other hand, under the condition that no avalanche breakdown takes place due to the concentration of the electric field at the pn junction between the n−-type semiconductor layer and the p+-type semiconductor region and the concentration of the electric field at the interface between the n−-type semiconductor layer and the n+-type semiconductor region, the blocking voltage (voltage withstanding capability, to say in another way) is ultimately determined by the avalanche breakdown brought about by the concentration of the electric field at the interface between the n−-type semiconductor layer and the dielectric layer immediately below the n+-type semiconductor region.
In order to implement the semiconductor device so that the condition mentioned above is satisfied, it is required to set sufficiently long the distance between the p+-type semiconductor region and the n+-type semiconductor region while optimizing the thickness d and the impurity concentration of the n−-type semiconductor layer.
In this conjunction, it is generally known that the concentration of the electric field at the interface between the n−-type semiconductor layer and the dielectric layer just satisfies the condition for the avalanche breakdown when depletion has reached the surface of the n−-type semiconductor layer from the interface between the n−-type semiconductor layer and the dielectric layer, as is described in the aforementioned patent specification by reference to FIG. 56. In that case, the depletion layer reaches the n−-type semiconductor layer with the whole n−-type semiconductor layer being depleted.
Under the condition mentioned above, the blocking voltage V can be given by the following expression:V=Ecr·(d/2+∈2·t0/∈3)  (4)where Ecr represents a critical electric field intensity at which the avalanche breakdown takes place. The thickness of the n+-type semiconductor region is neglected.
Further, as is described in the aforementioned patent specification by reference to FIG. 57, in the distribution of electric field intensity in the vertical direction at the section located immediately below the n+-type semiconductor region, the electric field intensity at the boundary between the n−-type semiconductor layer and the dielectric layer (location distanced by d from the origin toward the electrode) attains the critical electric field intensity Ecr.
In the case where the n−-type semiconductor layer is formed of silicon with the dielectric layer being formed of a silicon oxide film, the values of the distance d and the thickness t0 adopted in calculating the blocking voltage V of the semiconductor device in accordance with the expression (4) are generally as follows:d=4×10−4t0=2×10−4
The critical electric field intensity Ecr is subjected to the influence of the thickness d of the n−-type semiconductor layer. In general, however, the critical electric field intensity Ecr may well be 4×10−5. Accordingly, in accordance with the expression (4), the blocking voltage V can be determined as follows:V=320 V  (5)provided that Ecr=4×10−5, ∈2=11. 7, ∈3=3.9.
Thus, when the thickness d of the n−-type semiconductor layer is increased by 1 μm, a voltage increment ΔV is determined as follows:ΔV=Ecr×0.5×10−4=20 [V]  (6)
On the other hand, when the thickness t0 of the dielectric layer increases by 1 μm, the voltage increment ΔV is determined as follows:ΔV=Ecr×11.7×10−4/3.9=120 [V]  (7)
As can be seen from the results of calculations (6) and (7), the blocking voltage (voltage withstanding capability) can be increased by forming thicker the dielectric layer than n−-type semiconductor layer. In other words, the blocking voltage or voltage withstanding capability can be increased or enhanced more effectively by increasing the thickness of the evaporation in three layers.
In this conjunction, it is further noted that difficulty is encountered in increasing the thickness of the n−-type semiconductor layer because the trench etching process for forming a deeper trench is required, which demands development of novel etching technique.
However, when the thickness t0 of the dielectric layer is increased, extension x of the additional depletion layer decreases, reducing the RESURF effect. In other words, concentration of the electric field increases at the pn junction between the p+-type semiconductor region and the n−-type semiconductor layer, resulting in that the blocking voltage or voltage withstanding capability of the semiconductor device is limited by the avalanche breakdown taking place at the pn junction.
As is apparent from the foregoing, the dielectric separation type semiconductor device known heretofore suffers a problem that the blocking voltage or voltage withstanding capability of the semiconductor device is limited in dependence on the thickness t0 of the dielectric layer and the thickness d of the n−-type semiconductor layer.